IARU Amateur Satellite Frequency Coordination
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IARU Amateur Satellite Frequency Coordination |
| Inspire2 | Updated: 22 Jun 2015 | Responsible Operator | Anthony Monger VK2KZ | |
| Supporting Organisation | QB50 & The University of Sydney | |||
| Contact Person | a.monger@physics.usyd.edu.au.nospam | |||
| Headline Details: In addition to the common science package for QB50, the i-INSPIRE satellite will carry three scientific instruments for our own science mission. Except the imager, NanoSpec and radiation counter are designed for this mission. During the mission life-time, we will also demonstrate the nanothruster and the system-on-chip technology developed at the University of Sydney 1. NanoSpec. NanoSpec II is a diffraction limited single-mode fibre (SMF) fed spectrograph based upon the PIMMS#0 concept described by one of the design team. The concept is inspired by the efficient multi-mode to single-mode conversion of the photonic lantern. The photonic lantern enables an arbitrary input to compact efficient lantern diffraction limited providing maximum resolution and throughput in the most compact configuration possible. This allows for an extremely compact design and reduces complexities in alignment and construction, making it suitable for use in a small satellite. 2. Radiation Counter. To monitor the radiation level during the satellite mission life time. 3. Charge Exchange Thruster (CXT). The CXT is an electric powered ion propulsion system, providing thrust by the acceleration of ions along a potential difference on the order of 10 kV. The novel characteristic of the CXT is that there is no need to neutralize the exhaust particles. This gives the CXT a great advantage over conventional designs that require large electron guns to neutralize the exhaust ions. The CXT also has an extremely simple and robust design. These characteristics allow the CXT to be miniaturized for nanosatellite missions. 4. System-on-Chip (SoC). The on-board computer comes with two computing engines, a MSP430 microcontroller as the main OBC and an FPGA. We will use a Spartan 6 FPGA to demonstrate some computation-intensive algorithms, such as ADCS, encryption, compression and so on. Together with the SoC, a Network-on-Chip architecture will be implemented, which allows to interface the IP cores efficiently. Planning a UHF 9k6 BPSK downlink. ** A downlink on 436.330MHz has been coordinated** | ||||
| Application Date: | 29 Nov 2013 | Freq coordination completed on | 16 Jun 2015 | |
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